 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| QST104 Capacitive touch sensor device 4 keys with individual key state outputs or I2C interface Features Patented charge-transfer design Up to 4 independent QTouchTM keys supported Individual key state outputs or I2C interface Fully "debounced" results Patented AKSTM Adjacent Key Suppression Self-calibration and auto drift compensation Spread-spectrum bursts to reduce EMI Up to 13 general-purpose outputs ECOPACK(R) (RoHS compliant) package LQFP32 (7x7 mm) Description The QST104 is the ideal solution for the design of capacitive touch sensing user interfaces. Touch-sensitive controls are increasingly replacing electromechanical switches in home appliances, consumer and mobile electronics, and in computers and peripherals. Capacitive touch controls allow designers to create stylish, functional, and economical designs which are highly valued by consumers, often at lower cost than the electromechanical solutions they replace. The QST104 QTouchTM sensor IC is a pure digital solution based on Quantum's patented chargetransfer (QProxTM) capacitive technology. QTouchTM and QProxTM are trademarks of the Quantum Research Group. Table 1. Device summary Order code Feature QST104KT6 Operating supply voltage 2.4 to 5.5 V Supported interfaces Operating temperature Package Individual key state outputs or I2C Interface -40 to +85 C LQFP32 (7x7 mm) Applications This device specifically targets human interfaces and front panels for a wide range of applications such as PC peripherals, home entertainment systems, gaming devices, lighting and appliance controls, remote controls, etc. QST devices are designed to replace mechanical switching/control devices and the reduced number of moving parts in the end product provides the following advantages: Lower customer service costs Reduced manufacturing costs Increased product lifetime February 2008 Rev 2 1/45 www.st.com 1 Contents QST104 Contents 1 2 3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 QST touch sensing technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Spread-spectrum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Faulty and unused keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Detection threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Detection integrator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Fast positive recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Forced key recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Max On-Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Adjacent key suppression (AKSTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 4.2 4.3 4.4 4.5 Reset and power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5.1 4.5.2 4.5.3 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 KOUT outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Option descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General-purpose outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Communication packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.7 Supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/45 QST104 Contents 5 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 5.2 CS sense capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Sensitivity tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.1 5.2.2 5.2.3 Increasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Decreasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Key balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 5.4 5.5 5.6 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Crosstalk precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PCB layout and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 6.3 6.4 6.5 6.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 KOUTn/OPTn/GPOn pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6.1 6.6.2 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.7 6.8 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I2C control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 8 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Device revision information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 9.2 Device revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Device revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3/45 Device overview QST104 1 Device overview The QST104 capacitive touch sensor IC is a pure digital solution based on Quantum's patented charge-transfer (QProxTM) capacitive technology. This technology allows users to create simple touch panel sensing electrode interfaces for conventional or flexible printed circuit boards (PCB/FPCB). Sensing electrodes are part of the PCB layout (copper pattern or printed conductive ink) and may be used in various shapes (circle, rectangular, etc.). By implementing the QProxTM charge-transfer algorithm, the QST104 detects finger presence (human touch) near electrodes behind a dielectric (glass, plastic, wood, etc.). Only one external sampling capacitor by channel is used in the measuring circuitry to control the detection. QST technology also incorporates advanced processing techniques such as drift compensation, auto-calibration, noise filtering, and Quantum's patented Adjacent Key SuppressionTM (AKSTM) to ensure maximum usability and control integrity. In order to meet environmental requirements, ST offers this device in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 4/45 QST104 Pin description 2 Pin description Figure 1. 32-pin package pinout GPO4/KOUT4/OPT4 (HS) GPO5/OPT5 (HS) IRQ/OPT6 (HS) I2C_SDA1) (HS) I2C_SCL1) (HS) RESET NC VDD_1 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 QST104KT6 20 19 18 17 9 10 11 12 13 14 15 16 GPO3/OPT3/KOUT3 (HS) GPO2/OPT2/KOUT2 (HS) GPO1/OPT1/KOUT1 (HS) GPO13 GPO12 GPO11 GPO10 GPO9 GPO8 GPO7 GPO6 SNSK_SCK4 SNS_SCK4 SNSK_SCK3 SNS_SCK3 SNSK_SCK2 (HS) 20 mA high sink capability (on N-buffer only) 1. An external pull-up is required on these pins. Table 2. Pin 1 Device pin description Pin name Type (1) PP (HS) Stand-alone mode function Key 4 output / BCD output 4 and MOD_0 option resistor I2C mode function If unused GPO4/OPT4/KOUT4 (2) 2 GPO5/OPT5 (2) PP (HS) MOD_1 option resistor VSS_1 VSS_2 VSS_3 VSS_4 VDD_2 SNS_SCK1 SNSK_SCK1 SNS_SCK2 General-purpose output 4 Option and IC address bit 2 resistor option resistor Open or General-purpose output 5 option resistor Interrupt line (active low) Open or option resistor Open Open I2C serial data I2C serial clock 3 OPT6/IRQ (2) PP/OD (HS) TOD (HS) TOD (HS) OM_0 option resistor 4 5 I2C_SDA(3) I2C_SCL(3) 5/45 Pin description Table 2. Pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 QST104 Device pin description (continued) Pin name Type (1) BD Stand-alone mode function Reset (active low) Not connected S S S S S S SNS SNS SNS SNS SNS SNS SNS SNS PP PP PP PP PP PP PP PP PP (HS) Supply voltage Ground voltage Ground voltage Ground voltage Ground voltage Supply voltage Key 1 sense pin to Cs Key 1 sense pin to Cs/Rs Key 2 sense pin to Cs Key 2 sense pin to Cs/Rs Key 3 sense pin to Cs Key 3 sense pin to Cs/Rs Key 4 sense pin to Cs Key 4 sense pin to Cs/Rs General-purpose output 6 General-purpose output 7 General-purpose output 8 General-purpose output 9 General-purpose output 10 General-purpose output 11 General-purpose output 12 General-purpose output 13 Key 1 output / BCD output 1 and MODE option resistor Key 2 output / BCD output 2 and AKS option resistor Key 3 output / BCD output 3 and LP option resistor Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open General-purpose output 1 Option and MODE option resistor resistor General-purpose output 2 Option and I2C address bit 0 resistor option resistor General-purpose output 3 Option and I2C address bit 1 resistor option resistor I2C mode function If unused 10nF capacitor to ground RESET NC VDD_1 VSS_1 VSS_2 VSS_3 VSS_4 VDD_2 SNS_SCK1 SNSK_SCK1 SNS_SCK2 SNSK_SCK2 SNS_SCK3 SNSK_SCK3 SNS_SCK4 SNSK_SCK4 GPO6 GPO7 GPO8 GPO9 GPO10 GPO11 GPO12 GPO13 GPO1/OPT1/KOUT1 (2) 31 GPO2/OPT2/KOUT2 (2) PP (HS) 32 GPO3/OPT3/KOUT3 (2) PP (HS) 1. S: supply pin, BD: bidirectional pin, SNS: capacitive sensing pin, PP: Output push-pull, OD: Output open-drain, TOD: Output true open-drain and HS: 20mA high sink (on N-buffer only) 2. During the reset phase, these pins are floating and the state depends on the option resistor. 3. An external pull-up is required on these pins. 6/45 QST104 QST touch sensing technology 3 3.1 QST touch sensing technology Functional description QST devices employ bursts of charge-transfer cycles to acquire signals. Burst mode permits low power operation, dramatically reduces RF emissions, lowers susceptibility to RF fields, and yet permits excellent speed. Signals are processed using algorithms pioneered by Quantum which are specifically designed to provide reliable, trouble-free operation over the life of the product. The QST switches and charge measurement hardware functions are all internal to the device. An external CS capacitor accumulates the charge from sense-plate CX, which is then measured. Larger values of CX cause the charge transferred into CS to rise more rapidly, reducing available resolution. As a minimum resolution is required for proper operation, this can result in dramatically reduced gain. Larger values of CS reduce the rise of differential voltage across it, increasing available resolution by permitting longer QST bursts. The value of CS can thus be increased to allow larger values of CX to be tolerated. The device is responsive to both CX and CS, and changes in either can result in substantial changes in sensor gain. Figure 2. QTouchTM measuring circuitry CT (~5 pF) SNSK_SCKn Sense capacitor CS (a few nF) Earth SNS_SCKn Cx (~20 pF) Ai12569 3.2 Spread-spectrum operation The bursts operate over a spread of frequencies, so that external fields will have minimal effect on key operation and emissions are very weak. Spread-spectrum operation works with the Detection Integrator mechanism (DI) to dramatically reduce the probability of false detection due to noise. 7/45 QST touch sensing technology QST104 3.3 Faulty and unused keys Any sensing channel that does not have its sense capacitor (CS) fitted is assumed to be either faulty or unused. This channel takes no further part in operation unless a Mastercommanded recalibration operation shows it to have an in-range burst count again. Faulty, unused or disabled keys are still bursted but not processed to avoid modifying the sensitivity of active keys. This is important for sensing channels that have an open or short circuit fault across CS. Such channels would otherwise cause very long acquire bursts, and in consequence would slow the operation of the entire QST device. To optimize touch response time and device power consumption, if some keys are not used, we recommend to try suppressing the ones which belong to the same burst. Bursts which do not have any keys implemented will then not be processed. 3.4 Detection threshold levels The key capacitance change induced by the presence of a finger is sensed by the variation in the number of charge transfer pulses to load the capacitor. The difference in the pulse count number is compared to a threshold in order to detect the key as pressed or not. Two different thresholds, one for detection and one for the end of detection, create an hysteresis in order to prevent erratic behavior. The default threshold levels and hysteresis values are described inSection 6.5: Capacitive sensing characteristics on page 33. 3.5 Detection integrator filter Detect Integrator (DI) filter mechanism works together with spread spectrum operation to dramatically reduce the effects of noise on key states. The DI mechanism requires a specified number of measurements that qualify as detections (and these must occur in a row) or the detection will not be reported. In a similar manner, the end of a touch (loss of signal) also has to be confirmed over several measurements. This process acts as a type of "debounce" mechanism against noise. The default DI value for confirming start of touch and end of touch is described in Section 6.5: Capacitive sensing characteristics on page 33. 3.6 Self-calibration On power-up, all keys are self-calibrated to provide reliable operation under almost any conditions. The calibration phase is used to compute a reference value per key which is then used by the process determining if a key is touched or not. The reference is an average of 8 single acquisitions. As a result, the calibration time of the system can be simply calculated using the following formula: tCAL = 8 * Burst_Period. The methodology used to measure the burst period is described in application note AN2547. For a maximum calibration duration (tCAL), please refer to Section 6.5: Capacitive sensing characteristics on page 33. 8/45 QST104 QST touch sensing technology 3.7 Fast positive recalibration The device autorecalibrates a key when its signal reflects a decrease in capacitance higher than a fixed threshold (PosRecalTh) for a defined number of acquisitions (PoseRecalI). 3.8 Forced key recalibration A recalibration of the device may be issued at any time by sending to the QST device the appropriate I2C command or by tying the RESET pin to ground. It is possible to recalibrate independently any individual key using an I2C command. 3.9 Max On-Duration The device can time out and automatically recalibrate each key independently after a fixed duration of continuous touch detection. This prevents the keys from becoming `stuck on' due to foreign objects or other sudden influences. This is known as the Max On-Duration feature. After recalibration, the key will continue to operate normally, even if partially or fully obstructed. Max On-Duration works independently per channel: a timeout on one channel has no effect on another channel. Infinite timeout is useful in applications where a prolonged detection can occur and where the output must reflect the detection no matter how long. In infinite timeout mode, the designer should take care to ensure that drift in CS, CX, and VDD do not cause the device to remain "stuck on" inadvertently even when the touching object is removed from the sense field. Timeout durations are not accurate and can vary substantially depending on VDD and temperature values, and should not be relied upon for critical functions. 3.10 Drift compensation Signal drift can occur because of changes in CX, CS, and VDD over time. Depending on the CS type and quality, the signal may vary substantially with temperature and veiling. If keys are subject to extremes of temperature or humidity, the signal can also drift. It is crucial that drift be compensated, otherwise false detections, non detections, and sensitivity shifts will follow. Drift compensation slowly corrects the reference level of each key while no detection is in effect. The rate of reference adjustment must be performed slowly or else legitimate detections can also be ignored. The device compensates drift on each channel independently using a maximum compensation rate to the reference level. Once a touch is sensed, the drift compensation mechanism ceases since the signal is legitimately high, and therefore should not cause the reference level to change. The signal drift compensation is "asymmetric": the reference level compensates drift in one direction faster than it does in the other. Specifically, it compensates faster for increasing signals than for decreasing signals. Decreasing signals should not be compensated for quickly, since an approaching finger could be compensated for partially or entirely while approaching the sense electrode. However, an obstruction over the sense pad, for which the sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially elevated reference level and thus become insensitive to touch. In this latter case, the sensor will compensate for the object's removal very quickly, usually in only a few seconds. 9/45 QST touch sensing technology Caution: QST104 When only one key is enabled or if keys are very close together, the common drift compensation must be disabled or its rate must be reduced to ensure correct device operation. 3.11 Adjacent key suppression (AKSTM) Adjacent key suppression (AKSTM) is a Quantum-patented feature which prevents multiple keys from responding to a single touch. This can happen with closely spaced keys, or a scroll wheel that has buttons very near it. The QST104 supports two AKS modes: Locking AKS Once a key is considered as "touched", all other keys are locked in an untouched state. To unlock these keys, the touched key must return to an untouched state. Then, the key having the lowest key ID number is declared as the "touched" one. Unlocking AKS On each acquisition, the signal strengths from each key are compared and the key with the highest signal level is declared as the "touched" one. In I2C mode, up to 8 AKS groups can be specified. Note: All keys belonging to the same AKS group must have the same AKS mode. 10/45 QST104 Device operating modes 4 4.1 Device operating modes Reset and power-up At power-up, the device configures itself according to the pull-up or pull-down option resistors present on pins OPT1 to OPT6. The device start-up and configuration may take up to tSetup. When the power is established, it is possible to force a new device configuration by applying a negative pulse on the RESET pin. The RESET pin is a bidirectional pin with an internal pull-up. The line is forced low when the device resets itself (through an IC command, for example). A 10nF capacitor is recommended on the RESET pin to ensure reliable start-up and noise immunity. 4.2 Burst operation The device operates in "Burst" mode. Each key touch is acquired using a burst of chargetransfer sensing pulses whose count varies depending on the value of the sense capacitor CS and the load capacitance CX. In Low Power mode, the device sleeps in an ultra-low current state between bursts to conserve power. 4.3 Low power mode In order to reduce the device power consumption, the QST family include scalable low power modes. Standard low power mode When the device is in standard low power mode, a window with very low power consumption is inserted between the acquisition of the last active key and the following acquisition of the first active key. This window duration is programmable as the 'sleep duration time'. Note that the sleep window insertion is cancelled in the following conditions: - - If a change is detected on a key, in order to speed up the DI process, the sleep window insertion is skipped until the end of the DI process. In I2C mode, when a key change is actually detected and reported with a negative pulse on the IRQ pin. In this case, the low power mode is disabled until a command is received from the host. Inside an I2C command, between the Write and the Read I2C frames, the sleep period is skipped. - Free run in detect The behavior in this mode is the same as in the standard low power mode except that the sleep window insertion is always skipped if any of the active keys is detected as touched. This is useful to improve the wheel response time. 11/45 Device operating modes QST104 Deep Sleep mode In Deep Sleep mode, the device enters a very low power mode indefinitely. The device resumes its operations after receiving an I2C frame with any address or a reset. Caution: If an I2C frame is received while in Sleep or Deep Sleep mode, the device wakes up but does not acknowledge the frame (even if it has an I2C frame with the device address). The host must therefore send again the frame until it is taken in account and acknowledged. 4.4 Mode selection The device options are configured by connecting pull-up or pull-down resistors on OPTn pins. The device operating mode is selected using option pin 1 (OPT1) while the device settings are configured using option pins OPT2 to OPT6 (Table 3). Option pins are sampled at power-up and after a reset. To fit most applications, the QST104 device offers two different operating modes: Stand-alone mode This mode allows the user to simply replace existing mechanical switches with a capacitive sensing solution. It is designed for maximum flexibility and can accommodate most popular sensing requirements via option resistors (AKS, Low power, Max On-Duration and output modes). In this mode, the 4 output pins reflect the status of the 4 sensing channels. I2C mode In this mode, which is the most open one, the device is driven using the I2C interface. To avoid polling, the QST device features an output interrupt pin (IRQ). The IRQ line reports all key changes to the Master device. The QST (Slave) device can drive up to 13 general-purpose outputs. Table 3. Operating modes Option resistor function OPT1: Mode selection OPT2 Pin OPT1 is high at start-up Stand-alone mode Pin OPT1 is low at start-up I2C mode AKS ADD0 OPT3 LP ADD1 OPT4 OPT5 OPT6 OM MOD_0 MOD_1 ADD2 Unused Unused 4.5 Stand-alone mode This mode allows the user to simply replace existing mechanical switch interface with a capacitive sensing solution. It is designed for maximum flexibility and can accommodate most popular sensing requirements via option resistors (see Figure 3). 4.5.1 Main features Pins KOUT1 to KOUT4 directly reflect the state of keys Selectable global adjacent key suppression (AKSTM) Selectable sleep duration Selectable Max On-Duration values Selectable BCD mode 12/45 QST104 Figure 3. Stand-alone mode typical schematic VDD VUNREG 4.7F 2.4~5.5V Volt. Reg. 4.7F 100nF 100nF Device operating modes 8 13 Keep these parts close to IC RS4 Key4 10k 21 VDD_1 VDD_2 RESET 6 To Host 10nF SNSK_SCK4 SNS_SCK4 SNSK_SCK3 SNS_SCK3 MOD_1 SNSK_SCK2 SNS_SCK2 SNSK_SCK1 LP/KOUT3 32 CS4 20 RS3 Key3 10k 19 OM 3 1M CS3 VDD VSS VDD VSS KOUT4 VDD VSS KOUT3 VDD VSS 18 2 RS2 Key2 10k 17 1M CS2 16 MOD_0/KOUT4 1 RS1 Key1 10k 15 1M CS1 14 SNS_SCK1 1M AKS/KOUT2 31 Binary- 1M KOUT2 coded Output VDD Mode VSS KOUT1 VDD MODE/KOUT1 30 1M VSS_1 9 VSS_2 10 VSS_3 11 VSS_4 12 Ai12572 4.5.2 KOUT outputs KOUTn outputs directly reflect the state of keys. These pins are push-pull outputs. Under RESET, these pins are floating and their state depends on the option resistors. Pins KOUTn are active high meaning that when a key is "touched", the corresponding KOUT pin outputs a `1'. 13/45 Device operating modes QST104 4.5.3 Option descriptions Adjacent key suppression (AKSTM) The QST104 features an adjacent key suppression (AKSTM) function. This function is enabled using the AKS option resistor (OPT2) in standard output mode as described in Table 4. In BCD output mode, the AKS function is always enabled, regardless of the option resistor configuration. Table 4. AKS truth table Description Disabled Global locking AKS on all available keys OPT2/AKS VSS VDD Low Power mode option This option resistor (OPT3) selects whether the device is always sensing the keys or if a low power consumption phase is introduced between bursts as described in Table 5. In Low Power mode, a very low consumption (sleep) phase of 100ms is inserted between two consecutive bursts. This significantly reduces the overall consumption of the device. Sleep duration is not accurate and can vary substantially depending on VDD and temperature values. Note: In Low Power mode, the response time is increased. Table 5. Low power (LP) mode truth table Description Free running mode 100ms sleep duration OPT3/LP VSS VDD Max On-Duration There are four recalibration timing options ("Max On-Duration"). The recalibration option resistors (OPT4 and OPT5) control how long it takes for a continuous detection to trigger a recalibration on a key as described in Table 6. When such an event occurs, only the "stuck" key is recalibrated. Table 6. Max On-Duration (MOD) truth table Description Infinite 60s 20s 10s OPT4/MOD_0 OPT5/MOD_1 VSS VSS VDD VDD VSS VDD VSS VDD 14/45 QST104 Device operating modes Output mode option The QST104 offers several outputs mode to fit any existing application. Table 7. OPT6/OM VSS VDD Output mode (OM) truth table Description Individual key state output mode: One output per sensing channel BCD output mode: Binary-coded touched key number (see Table 8)(1) 1. In BCD mode, the AKS function is always active. Table 8. Binary code truth table Description All released Key 1 pressed Key 2 pressed Key 3 pressed Key 4 pressed Not used KOUT4 KOUT3 KOUT2 KOUT1 0 0 0 0 0 0 0 0 0 1 Other 0 0 1 1 0 0 1 0 1 0 15/45 Device operating modes QST104 4.6 I2C mode The I2C mode offers the largest configurability and functionality of the QST104. 4.6.1 Main features 13 general-purpose outputs Configuration of up to 8 AKS groups Additional low power modes Accessible internal capacitive sensing parameters Continuous range of Max On-Duration 16/45 QST104 Figure 4. I2C mode typical schematic VDD VUNREG 2.4~5.5V Volt. Reg. Device operating modes VDD 100nF 4.7F 4.7F 100nF 2.7k VDD_1 Keep these parts close to IC VDD_2 I2C_SCL I2C_SDA IRQ RESET 5 4 3 6 2.7k 8 13 10k RS4 Key4 10k 21 SNSK_SCK4 SNS_SCK4 SNSK_SCK3 SNS_SCK3 SNSK_SCK2 SNS_SCK2 SNSK_SCK1 SNS_SCK1 To Host MCU To Host 10nF CS4 20 19 RS3 Key3 10k CS3 18 17 RS2 Key2 10k GPO13 GPO12 GPO11 GPO10 GPO9 GPO8 GPO7 GPO6 GPO5 ADD2/GPO4 29 28 27 26 25 24 23 22 2 GPO13 GPO12 GPO11 GPO10 GPO9 GPO8 GPO7 GPO6 GPO5 GPO4 VDD VSS GPO3 VDD VSS GPO2 VDD VSS GPO1 VSS CS2 16 15 RS1 Key1 10k CS1 14 1 1M ADD1/GPO3 32 1M ADD0/GPO2 31 1M MODE/GPO1 VSS_1 9 30 VSS_2 10 VSS_3 11 VSS_4 12 1M Ai12573 4.6.2 General-purpose outputs I2C mode allows to drive up to 13 general-purpose outputs. These output pins are configured in output push pull mode 0 by default. Their state can be changed using the SET_GPIO_STATE I2C command. 17/45 Device operating modes Figure 5. Optional LED schematic VUNREG QST104 R GPOn C (10 nF) Ai12570 4.6.3 IRQ pin The IRQ pin is an open drain output with an internal pull-up. It can be used to inform the Master device about any change in the key status. The IRQ line is pulled low every time the state of any of the enabled keys changes. This includes any change in the touch state of the key, a faulty key or a new calibration of one or more keys. The reported changes may then be accessed by the Master device by using the GET_KEY_STATE command. To improve communication response time, this signal suspends Low Power mode until the Master device has issued a communication with the QST device. 4.6.4 Communication packet The communication between the Master device and the QST104 (Slave) consists of two standard I2C frames. The first frame is sent by the Master device using the QST104 device address with the write bit set. The data bytes consist of the command byte which is eventually followed by the parameters and a checksum byte. The second one is sent by the Master device using the QST104 device address with the write bit reset. The QST104 completes the frame with data according to the command previously sent by the Master device. The device finishes the frame by sending a checksum byte for communication integrity verification. If the read frame is omitted, the command may not be taken into account. To initiate the communicate with the QST104, the Master device must send the GET_DEVICE_INFO command in order to unlock access to all the other commands. 18/45 QST104 Device operating modes 4.6.5 I2C address selection The QST104 slave address is programmable using the option resistors mapped on pins OPT2 to OPT4 (see Table 9). Table 9. IC address versus option resistor I2C Address ADD[6:3] ADD2 0 0 0 0 0101 1 1 1 1 0 0 1 1 0 1 0 1 0x2C 0x2D 0x2E 0x2F ADD1 0 0 1 1 ADD0 0 1 0 1 Hex value 0x28 0x29 0x2A 0x2B Option configuration OPT4 VSS VSS VSS VSS VDD VDD VDD VDD OPT3 VSS VSS VDD VDD VSS VSS VDD VDD OPT2 VSS VDD VSS VDD VSS VDD VSS VDD 4.7 Note: Supported commands Table 10 lists the supported IC commands and available arguments. For more information on the supported commands and I2C protocol, please refer to the QST standard communication protocol reference manual. Table 10. Supported commands I2C commands CALIBRATE_KEY (All keys) Write Read 0x98 ErrCode Forces the recalibration of all keys. ErrCode: Standard Error code (see Table 11) Description CALIBRATE_KEY (Single key) Write Read 0x9B KeyID Checksum ErrCode Forces the recalibration of a single key. KeyId: Binary-coded key number (see Table 14) ErrCode: Standard Error code (see Table 11) GET_DEBUG_INFO Write 0xF7 KeyID Checksum 0x0B KeyDbgState RefMSB RefLSB BCMSB BCLSB Checksum Returns the debug info of the single KeyID channel. KeyDbgState: Current Key Debug state (see Table 19) RefMSB: Reference Count MSB RefLSB: Reference Count LSB BCMSB: Burst Count MSB BCLSB: Burst Count LSB Read 19/45 Device operating modes Table 10. Supported commands (continued) I2C commands GET_DEVICE_INFO Write Description QST104 Read Returns the QST104 device version and ASCII-coded device name. This command must be sent first to enable the communication flow. 0x15 MainVers SubVers MainVers: Device main version NbSCkey NbMCkey SubVer: Device sub-version `Q' 'S' `T' `1' `0' `4' NbSCkey: 0x04 single-channel keys Checksum NbMCkey: 0x00 multi-channel keys Q S T 1 0 4: ASCII-coded device name 0x85 GET_KEY_ERROR Write Read 0xC4 0x11 KeyError1 KeyError2 ... KeyError4 CheckSum Returns the error information on each key. KeyErrorN: KeyError byte description (see Table 12) GET_KEY_STATE Write Read 0xC1 0x03 AllKeyState KeyError Checksum Returns the state of all keys. AllKeyState: Touched/untouched state for all 4 keys. Refer to Table 13: AllKeyState. KeyError: Refer to Table 12: KeyError byte description GET_PROTOCOL_VERSION Write Read 0x80 0x07 MainVers SubVer I2CSpeed Checksum Returns the QST104 protocol version. MainVers: Protocol main version SubVer: Protocol sub-version I2CSpeed: 0x00 (100 kHz maximum) RESET_DEVICE Write Read 0xFD ErrCode Restarts the device (options Read and Calibration) after reading the ErrCode (see Table 11). SET_DETECT_INTEGRATORS Write 0x03 0x04 0x00 DI EDI PosRecaII CheckSum Sets the detection, End Of Detection and Positive Recalibration Integrators for all keys. DI: Detection Integrator 1) 3) EDI: End of Detection Integrator 1) 3) PosRecaII: Positive Recalibration Integrator 1) 3) ErrCode: Standard Error code (see Table 11) Read ErrCode SET_GPIO_STATE Write Read 0x08 0x02 GPOState1 GPOState2 Checksum ErrCode Controls the state of the general-purpose outputs. GPOStateN: State of general-purpose outputs (see Table 16) ErrCode: Standard Error code (see Table 11) 20/45 QST104 Table 10. Supported commands (continued) I2C commands SET_KEY_ACTIVATION (see Note 4) Write Read 0x97 KeyActivation Checksum ErrCode Device operating modes Description Enables or disables a single key. KeyActivation: Byte containing the key number selection and requested state. ErrCode: Standard Error code (see Table 11) SET_KEY_GROUP 0x00 0x09 AKSGrpMode Key1Grp Key2Grp ...Key8Grp CheckSum ErrCode Defines the AKS groups for each key. AKSGrpMode: AKS mode selection of each group (see Table 17) KeynGrp: AKS group selection for key n (see Table 18) ErrCode: Standard Error code (see Table 11) Write Read SET_LOW_POWER_MODE Write Read 0x92 LowPowerMode Checksum ErrCode Selects standard or Low Power mode. LowPowerMode: Configure Low Power mode (see Table 15) ErrCode: Standard Error code (see Table 11) SET_MAX_ON_DURATION Write Read 0x8A MaxOnDuration Checksum ErrCode Sets the maximum detected ON time before triggering an automatic recalibration. MaxOnDuration: Time, in second (0 for infinite) ErrCode: Standard Error code (see Table 11) SET_SCKEY_PARAMETERS Write 0x01 0x04 0x00 DeTh EofDeTh PosRecalTh Checksum ErrCode Sets the Detection, End Of Detection and Positive Recalibration Thresholds for a single key. DeTh: Detection Threshold 1) 2) EofDeTh: End of Detection Threshold 1) 2) PosRecalTh: Positive Recalibration Threshold 1) 2) ErrCode: Standard Error code (see Table 11) Read Note: 1 2 3 4 See Section 6.5: Capacitive sensing characteristics on page 33 for default values. The value is a signed character (0x80...0x7F <=> -128 ... +128). The value is an unsigned number (0x00..0xFF <=> 0 ... 255). Enabling or disabling keys triggers a new calibration of all enabled keys. 21/45 Device operating modes QST104 Error codes Table 11 lists the I2C error codes. Table 11. ErrCode 0x01 0x83 0x85 0xA1 0xA3 0xE0 No Error Command not supported Parameter not supported Parity Error Checksum Error Initialization process (GET_FIRMWARE_INFO command not received) ErrCode Description KeyError byte description Table 12. Bit 7 Key State KeyError byte description Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Key error codes Bit 0 Key state (Bit 7) When set to `1', the corresponding key is touched. This bit is always cleared for the GET_KEY_STATE command. Key error codes (Bits 2:0) When answering the GET_KEY_STATE command, the key error code corresponds to the error codes of all the keys ORed toghether. When answering the GET_KEY_ERROR command, each key error code describes the errors of one defined key. Bit 0: When set to `1', calibration in progress Bit 1: When set to `1', maximum count reached Bit 2: When set to `1', minimum count not reached All key state description Table 13. Bit 7 0 AllKeyState Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 Key 4 State Key 3 State Key 2 State Key 1 State Key n state When set to `1', the corresponding key is touched. 22/45 QST104 Device operating modes Key activation description Table 14. Bit 7 Key Activation KeyActivation Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 Key ID (binary coded) Key activation (Bit 7) 0: Key enabled 1: Key disabled Key identifier (Bits 3:0) 0000: All keys 0001: Key 1 0010: Key 2 0011: Key 3 0100: Key 4 Low power mode description Table 15. Bit 7 0 SetLowPower Bit 6 Free Run in Detect Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sleep Duration Factor Free Run in Detect (Bit 6) 0: Low Power mode is always enabled, whatever the state of the keys. 1: Low Power mode is automatically suspended when any key is in Detect state. Low Power mode is automatically resumed when no key is in Detect state. Sleep Duration Factor (Bits 5 to 0) 0x00 or 0x20 to 0x3E: Low power mode is disabled. 0x01 to 0x19: Low Power mode. The sleep duration is `Sleep Duration Factor' x 20 milliseconds (20 ms to 500 ms) 0x3F: Deep Sleep mode is entered immediately. Only a reset or an I2C frame with the correct device address allows exiting Deep Sleep mode. Note: 1 2 When the device is in Sleep or Deep Sleep, any I2C bus activity will wake-up the device. The I2C QST device address is not acknowledged but forces the QST device to exit from Low Power mode. The Master device will have to repeat the command to ensure that it is taken in account. 23/45 Device operating modes QST104 GPO state description Table 16. Byte GPOState1 GPOState2 GPOState Bit 7 GPO 8 state 0 Bit 6 GPO 7 state 0 Bit 5 GPO 6 state 0 Bit 4 GPO 5 state GPO 13 state Bit 3 GPO 4 state GPO 12 state Bit 2 GPO 3 state GPO 11 state Bit 1 GPO 2 state GPO 10 state Bit 0 GPO 1 state GPO 8 state GPOState Defines the state of the selected general-purpose output pin. For more information, see Section 4.6.2: General-purpose outputs on page 17. 0: GPO state is `0' 1: GPO state is `1' AKS group mode description Table 17. Bit 7 AKSGrp8 Mode AKSGrpnMode Bit 6 AKSGrp7 Mode Bit 5 AKSGrp6 Mode Bit 4 AKSGrp5 Mode Bit 3 AKSGrp4 Mode Bit 2 AKSGrp3 Mode Bit 1 AKSGrp2 Mode Bit 0 AKSGrp1 Mode AKSGrpnMode Defines the type of AKS for the Group n: 0: Locking AKS First key pressed within the group locks out all other keys. 1: Unlocking AKS Most heavily pressed key (highest signal level) is selected over all other keys in the group. AKS group selection description Table 18. Bit 7 Grp8 KeynGrp Bit 6 Grp7 Bit 5 Grp6 Bit 4 Grp5 Bit 3 Grp4 Bit 2 Grp3 Bit 1 Grp2 Bit 0 Grp1 Grpx The selected key is a member of AKS Group x. 24/45 QST104 Device operating modes Key debug state description Table 19. KeyDbgState Description On-going calibration Key released Key touched Key in error Key calibration filter triggered (PosRecalI) Key detection filter triggered (DI) Key end of detection filter triggered (EDI) Value 0x01 0x02 0x04 0x08 0x11 0x14 0x24 25/45 Design guidelines QST104 5 5.1 Design guidelines CS sense capacitor The CS sense capacitors accumulate the charge from the key electrodes and determine sensitivity. Higher values of CS make the corresponding sensing channel more sensitive. The values of CS can differ for each channel, permitting differences in sensitivity from key to key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and placement differences and stray wiring capacitances. More stray capacitance on a sense trace will desensitize the corresponding key. Increasing the CS for that key will compensate for the loss of sensitivity. The CS capacitors can be virtually any plastic film or low- to medium-K ceramic capacitor. The normal CS range is 1nF to 50nF depending on the sensitivity required: larger values of CS require better quality to ensure reliable sensing. In certain circumstances the normal CS range may be exceeded. Acceptable capacitor types for most uses include PPS film, polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are not recommended. 5.2 Sensitivity tuning Sensitivity can be altered to suit various applications and situations on a channel-bychannel basis. The easiest and most direct way to impact sensitivity is to alter the value of each CS: more CS yields higher sensitivity. Each channel has its own CS value and can therefore be independently adjusted. 5.2.1 Increasing sensitivity Sensitivity can also be increased by using larger electrode areas, reducing panel thickness, or using a panel material with a higher dielectric constant. 5.2.2 Decreasing sensitivity In some cases the circuit may be too sensitive. Gain can be lowered further by a number of strategies: making the electrode smaller making the electrode into a sparse mesh using a high space-to-conductor ratio decreasing the CS capacitors 5.2.3 Key balance A number of factors can cause sensitivity imbalances. Notably, SNS wiring to electrodes can have differing stray amounts of capacitance to ground. Increasing load capacitance will cause a decrease in gain. Key size differences, and proximity to other metal surfaces can also impact gain. The keys may thus require "balancing" to achieve similar sensitivity levels. This can be best accomplished by trimming the values of the CS capacitors to achieve equilibrium. The RS resistors have no effect on sensitivity and should not be altered. Load capacitances to ground can also be added to overly sensitive channels to reduce their gain. These should be in the order of a few picofarads. 26/45 QST104 Design guidelines 5.3 Power supply If the power supply fluctuates slowly with temperature, the QST device compensates automatically for these changes with only minor changes in sensitivity. However, if the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. The power supply should be locally regulated, using a three-terminal regulator. If the supply is shared with another electronic system, care should be taken to ensure that the supply is free of digital spikes, sags and surges which can cause adverse effects. It is not recommended to include a series inductor in the power supply to the QST device. For proper operation, a 0.1 F or greater bypass capacitor must be used between VDD and VSS. The bypass capacitor should be routed with very short tracks to the device's VDD and VSS pins. The PCB should, if possible, include a copper pour under and around the device, but not extensively under the SNS lines. 5.4 ESD protection In normal environmental conditions, only one series resistor is required for ESD suppression. A 10 kOhm RS resistor in series with the sense trace is sufficient in most cases. The dielectric panel (glass or plastic) usually provides a high degree of isolation to prevent ESD discharge from reaching the circuit. RS should be placed close to the chip. If the CX load is high, RS can prevent total charge and transfer and as a result gain can deteriorate. If a reduction in RS increases gain noticeably, the lower value should be used. Conversely, increasing the RS can result in added ESD and EMC benefits, provided that the increase does not decrease sensitivity. 5.5 Crosstalk precautions Adjacent sense traces might require intervening ground traces in order to reduce capacitive cross bleed if high sensitivity is required or high values of delta-CX are anticipated (for example, from direct human touch to an electrode connection). In normal touch applications behind plastic panels, this is rarely a problem regardless of how the electrodes are wired. Higher values of RS will make crosstalk problems worse; try to keep RS to 22 kOhm or less if possible. In general try to keep the QST device close to the electrodes and reduce the adjacency of the sense wiring to ground planes and other signal traces; this will reduce the Cx load, reduce interference effects, and increase signal gain. The one and only valid reason to run ground near SNS traces is to provide crosstalk isolation between traces, and then only on an as-needed basis. 5.6 PCB layout and construction The PCB traces, wiring, and any components associated with or in contact with either SNS pin will become touch sensitive and should be treated with caution to limit the touch area to the desired location. Multiple touch electrodes connected to any sensing channel can be used, for example, to create control surfaces on both sides of an object. 27/45 Design guidelines QST104 It is important to limit the amount of stray capacitance on the SNS terminals, for example by minimizing trace lengths and widths to allow for higher gain without requiring higher values of CS. Under heavy delta-CX loading of one key, cross coupling to another key's trace can cause the other key to trigger. Therefore, electrode traces from adjacent keys should not be run close to each other over long runs in order to minimize cross-coupling if large values of delta-CX are expected, for example when an electrode is directly touched. This is not a problem when the electrodes are working through a plastic panel with normal touch sensitivity. For additional information on PCB layout and construction, please contact your local ST Sales Office for a list of available application notes. 28/45 QST104 Electrical characteristics 6 6.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25C, VDD = 5 V (for the 4.5V VDD 5.5 V voltage range) and VDD = 3.3 V (for the 3.0 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Figure 6. Pin loading conditions Output pin 29/45 Electrical characteristics QST104 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 7. Pin input voltage Input pin VIN 6.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 20. Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Maximum junction temperature Value -65 to +150 Unit C Table 21. Symbol Voltage characteristics Ratings Maximum value 7.0 (1)(2) Unit VDD - VSS Supply voltage VIN Input voltage on any pin VSS-0.3 to VDD+0.3 2000 500 V VESD(HBM) Electrostatic discharge voltage (Human Body Model) VESD(CDM) Electrostatic discharge voltage (Charge Device Model) 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN QST104 Table 22. Symbol IVDD IVSS Electrical characteristics Current characteristics Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink) Output current sunk by RESET pin IIO Output current sunk by output pin Output current source by output pin IINJ(PIN)(2) (3) (1) Maximum value 75 150 20 40 - 25 5 5 20 Unit mA Injected current on RESET pin Injected current output pin IINJ(PIN)(2) Total injected current (sum of all I/O and control pins) 1. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Operating conditions Table 23. Symbol VDD TA Operating supply voltage Operating temperature Operating conditions Feature Value 2.4 to 5.5 -40 to +85 Unit V C 31/45 Electrical characteristics QST104 6.4 Supply current characteristics Table 24. Symbol Supply current characteristics Parameter Conditions VDD = 2.4 V Min. Typ. (1) 1.71 2.17 3.35 158 215 355 75 99 156 1 A A A mA Max. Unit Average suppy current IDD (FR) Free Run mode VDD = 3.3 V VDD = 5 V IDD Average suppy current (Sleep 100ms Sleep mode 100ms) IDD Average suppy current (Sleep 500ms Sleep mode 500ms) IDD Halt Average suppy current Halt mode VDD = 2.4 V VDD = 3.3 V VDD = 5 V VDD = 2.4 V VDD = 3.3 V VDD = 5 V 1. The results are based on CS = 2.7nF and CX = 12.5pF Figure 8. IDD Sleep mode current characteristics 32/45 QST104 Electrical characteristics 6.5 Capacitive sensing characteristics Table 25. Symbol CS CX CT RS Sense capacitor Equivalent electrode capacitor Equivalent touch capacitor Serial resistance 5 10 22 External sensing components Parameter Min. Typ. Max. 100 100 Unit nF pF pF kOhm Table 26. Symbol tCAL tSetup DI DeTh EDI EofDeTh PosRecalI Capacitive sensing parameters Parameter Calibration duration Setup duration Detection integrator Detection threshold End of detection integrator End of detection threshold Positive recalibration integrator Positive recalibration threshold 0 -128 0 -128 0 1 1 0.1 0.1 0.1 0.1 0 0 0 0 20 100 2 -10 2 -8 2 6 Infinite 1 1 0.2 0.2 10 10 10 2 255 -1 255 -1 255 128 255 25.5 25.5 25.5 25.5 255 255 255 255 2000 Counts Min. Default Max. TBD Unit ms ms Counts Counts Counts Counts Counts Counts s s/level s/level s/level s/level PosRecalTh MaxOnDuration Max on-duration delay PosDiffDrift NegDiffDrift PosComDrift NegComDrift PosDriftI NegDriftI ComFact DiffFact BurstCount Positive differential drift compensation rate Negative differential drift compensation rate Positive common drift compensation rate Negative common drift compensation rate Positive drift integrator Negative drift integrator Common time step factor Differential time step factor Burst length 33/45 Electrical characteristics QST104 6.6 6.6.1 KOUTn/OPTn/GPOn pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 27. Symbol VIL VIH VHys IL CIO tf(IO)out tr(IO)out General characteristics Parameter Input low level voltage (1) Input high level voltage (1) Schmitt trigger voltage hysteresis(2) Input leakage current I/O pin capacitance Output high to low level fall time (2) Output low to high level rise time (2) CL = 50 pF Between 10% and 90% VSS VIN VDD 5 25 ns 25 Conditions Min. VSS -0.3 0.7x VDD 400 1 Typ. Max. 0.3x VDD VDD + 0.3 V Unit mV A pF 1. Not tested in production, guaranteed by characterization. 2. Data based on validation/design results. 6.6.2 Output pin characteristics Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 28. Symbol VOL (1) Output pin current Parameter Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 14) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 19) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time (Figure 17) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time Conditions IIO = +20mA IIO = +8mA IIO = -5mA IIO = -2mA VDD = 2.4V VDD = 3.3V IIO = +8mA IIO = -2mA IIO = +8mA IIO = -2mA VDD-0.9 VDD-0.8 0.6 VDD-1.5 VDD-0.8 0.5 V Min. Max. 1.3 0.75 Unit VOH(2) VOL(1)(3) VOH(2)(3) VOL(1)(3) VOH(2)(3) 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 22 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 22 and the sum of IIO (output and RESET pins) must not exceed IVDD.. 3. Not tested in production, based on characterization results. 34/45 VDD = 5V QST104 Electrical characteristics Figure 9. Typical VOL at VDD = 2.4 V VOL vs Iload @ VDD = 2.4 V HS pins Figure 10. Typical VOL vs VDD at Iload = 2 mA VOLvs VDD @Iload=2 mA HS Pins 120 1200 1000 800 -40C 25C 125C VOL[mV] -40C 25C 85C 125C 110 100 90 80 70 60 50 40 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 85C VOL [V] 600 400 200 0 0 2 4 6 8 10 12 14 16 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD [V] Iload [mA] Figure 11. Typical VOL at VDD = 3 V VOLvs Iload @ VDD = 3 V HS pins Figure 12. Typical VOL vs VDD at Iload = 8 mA VOL vs VDD@Iload = 8 mA HS Pins 1600 1400 1200 540 -40C 25C 85C 125C VOL[mV] -40C 25C 85C 125C 490 440 390 340 290 240 190 140 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 VOL [V] 1000 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 20 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD [V] Iload [mA] Figure 13. Typical VOL at VDD = 5 V VOL vs Iload @ VDD = 5 V HS pins Figure 14. Typical VOL vs VDD at Iload = 12 mA VOL vs VDD @Iload = 12 mA HS Pins 900 800 700 600 -40C 25C 85C 125C VOL[mV] 1040 940 840 740 640 540 440 340 240 140 -40C 25C 85C 125C VOL [V] 500 400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD [V] Iload [mA] 35/45 Electrical characteristics Figure 15. Typical VDD-VOH vs. Iload at VDD = 2.4 V VDD-VOH vs Iload @ VDD = 2.4 V HS Pins QST104 Figure 16. Typical VDD-VOH vs. VDD at Iload = 2 mA VDD-VOH vs VDD @Iload = 2 mA HS Pins 800 700 600 VDD-VOH [mV] 500 400 300 200 100 0 -40C 25C 85C 125C 800 700 600 VDD-VOH [mV] 500 400 300 200 100 0 -40C 25C 85C 125C 2. 8 3. 6 4 4. 4 5. 2 2. 4 3. 2 4. 8 2 Iload [mA] 4 VDD [V] Figure 17. Typical VDD-VOH vs. Iload at VDD = 3 V VDD-VOH vs Iload @ VDD = 3 V HS Pins Figure 18. Typical VDD-VOH vs. VDD at Iload = 4 mA VDD-VOH vs VDD @Iload = 4 mA HS Pins 1800 1600 1400 -40C 25C 85C 125C 1800 1600 1400 VDD-VOH [mV] 1200 1000 800 600 400 200 0 -40C 25C VDD -VOH [mV] 85C 125C 1200 1000 800 600 400 200 0 3 2. 6 3. 4 3. 8 4. 2 4. 6 5 0 2 Iload[mA] 4 6 VDD [V] Figure 19. Typical VDD-VOH vs. Iload at VDD = 5 V V DD-V OH vs Iload @ V DD = 5 V HS Pins 4500 4000 3500 VDD-VOH [mV] 3000 2500 2000 1500 1000 500 0 -40C 25C 85C 125C 0 2 4 6 8 10 12 14 Iload[mA] 36/45 5. 4 5. 6 QST104 Electrical characteristics 6.7 RESET pin TA = -40C to 125C, unless otherwise specified. Table 29. Symbol VIL VIH Vhys VOL RON tw(RSTL)out th(RSTL)in tg(RSTL)in RESET pin characteristics Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis(1) Output low level voltage(2) Pull-up equivalent resistor(3) Generated reset pulse duration External reset pulse hold time(4) Filtered glitch duration VDD = 5V VIN = VSS IIO = +2mA VDD = 5V VDD = 3V 30 Conditions Min. VSS - 0.3 0.7 x VDD 2 200 50 90(1) 90(1) 20 200 70 k s s ns Typ. Max. 0.3x VDD VDD + 0.3 V mV Unit V Internal reset sources 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Table 22: Current characteristics on page 31 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 37/45 Electrical characteristics QST104 6.8 I2C control interface Subject to general operating conditions for VDD, and TA unless otherwise specified. The QST104 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 30. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 IC characteristics 100 kHz speed Parameter Min. (1) 4.7 4.0 250 0 (2) 1000 ns 300 s s s pF Max. (1) Unit s ns tw(STO:STA) STOP to START condition time (bus free) 1. Data based on standard I2C protocol requirement, not tested in production. 2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of the SCL signal. Table 31. Symbol tW(IRQ) RIRQ IRQ specific pin characteristics (1) Parameter IRQ pulse width IRQ internal pull-up (2) VDD = 5V VDD = 3V Conditions Min. 10 100 120 300 Typ. Max. 15 140 k Unit s 1. For additional pin parameters, please use the pin description in Section 6.6: KOUTn/OPTn/GPOn pin characteristics on page 34. 2. The IRQ pull-up equivalent resistor is based on a resistive transistor. 38/45 QST104 Electrical characteristics Figure 20. Typical application with I2C bus and timing diagram VDD 4.7k I 2C VDD 4.7k 100 100 SDA SCL BUS QST device REPEATED START START tsu(STA) SDA tw(STO:STA) START tf(SDA) SCL tr(SDA) tsu(SDA) th(SDA) STOP th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) 39/45 Package mechanical data QST104 7 Package mechanical data Figure 21. 32-pin low profile quad flat package (7x7) outline Seating plane C A A2 A1 ccc C D D1 D3 24 17 16 A1 L L1 K c 0.25 mm Gage plane b 25 E3 E1 E 32 Pin 1 identification 9 1 8 e 5V_ME 40/45 QST104 Table 32. Dim. Min. A A1 A2 b c D D1 D3 E E1 E3 e L L1 K ccc 0.0 0.450 8.800 6.800 0.050 1.350 0.300 0.090 8.800 6.800 9.000 7.000 5.600 9.000 7.000 5.600 0.800 0.600 1.000 3.5 Tolerance (mm) 0.10 7.0 0.0 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.370 Typ. Max. 1.600 0.150 1.450 0.450 0.200 9.200 7.200 0.0020 0.0531 0.0118 0.0035 0.3465 0.2677 Min. Package mechanical data 32-pin low profile quad flat package mechanical data mm Typ. inches(1) Max. 0.0630 0.0059 0.0551 0.0146 0.3543 0.2756 0.2205 0.3543 0.2756 0.2205 0.0315 0.0236 0.0394 3.5 Tolerance (inches) 0.0039 7.0 0.0295 0.3622 0.2835 0.0571 0.0177 0.0079 0.3622 0.2835 1. Values in inches are converted from mm and rounded to 4 decimal digits. 41/45 Part numbering QST104 8 Part numbering Table 33. Example: Device type QST = Capacitive touch sensor Device sub-family 1: QTouch (3 to 5 V) Ordering information scheme QST 1 04 K T 6 Channel count Number of channels Pin count K: 32 pins Package T: LQFP (thin quad flat) Temperature range 6: -40C to +85C For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 42/45 QST104 Device revision information 9 9.1 Device revision information Device revision identification The marking on the right side of the second line (Line B) of the package top face identifies the device revision. Figure 22. Device revision identification (TQFP package) A QST104 QRG D B H00 E C F G H a J I K Table 34. Device revision identification Marking H00 Device revision V 1.0 The device revision can also be obtained using the GET_DEVICE_INFO I2C command. For more information, refer to Section 4.9: Supported commands on page 16. 9.2 Device revision history This section identifies the device deviations from the present specification for each device revision. 9.2.1 Revision 1.0 When the device enters low power mode, an additional sleep time is inserted after each burst, instead of once after every complete burst cycle. As a result, if only one burst is required, the sleep duration during low power mode is doubled. And if two bursts are required, the sleep duration is tripled. In standalone mode, the 100ms sleep duration low power becomes either a 200ms or 300ms sleep duration depending on the number of bursts required. In I2C mode, it is required to program a sleep duration for one half or a third of the desired sleep duration depending on the number of bursts required. GET_PROTOCOL_VERSION returns 0x01 as I2CSpeed byte while it should return 0x00 (maximum speed is 100 kHz). 43/45 Revision history QST104 10 Revision history Table 35. Date 26-Nov-2007 5-Feb-2008 Document revision history Revision 1 2 Initial release. Upgraded document status to datasheet. Changes 44/45 QST104 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 45/45 |
Price & Availability of QST104
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |